A device includes a memory array with first memory cell and second memory cell, and control logic, operatively coupled with the memory array, to cause a first threshold voltage (Vt) state read out of the first memory cell to be converted to a first integer value and a second Vt state read out of the second memory cell to be converted to a second integer value; index, within a decoding table using the first integer value and the second integer value, to determine a set of three logical bits; and output, as a group of logical bits to be returned in response to a read request, the set of three logical bits with a second set of logical bits corresponding to the first Vt state.