- Patent Title: Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system
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Application No.: US17692883Application Date: 2022-03-11
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Publication No.: US11861280B2Publication Date: 2024-01-02
- Inventor: In Huh , Jeong-hoon Ko , Hyo-jin Choi , Seung-ju Kim , Chang-wook Jeong , Joon-wan Chai , Kwang-il Park , Youn-sik Park , Hyun-sun Park , Young-min Oh , Jun-haeng Lee , Tae-ho Lee
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR 20190016842 2019.02.13
- The original application number of the division: US16788924 2020.02.12
- Main IPC: G06F30/33
- IPC: G06F30/33 ; G06N3/08

Abstract:
A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.
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