A semiconductor storage device includes a first input driver configured to receive a first signal from a memory controller, a second input driver configured to receive a chip enable signal from the memory controller, and a first control circuit. The first control circuit is configured to set the semiconductor storage device in an enabled state or a disabled state depending on whether or not the first signal which is received during a time period that starts with assertion of the chip enable signal and is prior to receipt of a command sequence, corresponds to a first chip address.