Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.