Invention Grant
- Patent Title: Gate-all-around integrated circuit structures having depopulated channel structures using selective bottom-up approach
-
Application No.: US17731110Application Date: 2022-04-27
-
Publication No.: US11862636B2Publication Date: 2024-01-02
- Inventor: Nicole Thomas , Ehren Mannebach , Cheng-Ying Huang , Marko Radosavljevic
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt, P.C.
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L29/06 ; H01L29/417 ; H01L29/423 ; H01L29/786 ; H01L29/66 ; H01L21/02 ; H01L21/8238

Abstract:
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.
Public/Granted literature
Information query
IPC分类: