Invention Grant
- Patent Title: Inner spacer structure and methods of forming such
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Application No.: US17243274Application Date: 2021-04-28
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Publication No.: US11862709B2Publication Date: 2024-01-02
- Inventor: Che-Lun Chang , Jiun-Ming Kuo , Ji-Yin Tsai , Yuan-Ching Peng
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/423 ; H01L29/49 ; H01L29/786 ; H01L21/02 ; H01L21/306 ; H01L21/8234

Abstract:
A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.
Public/Granted literature
- US20220352349A1 Inner Spacer Structure and Methods of Forming Such Public/Granted day:2022-11-03
Information query
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