Invention Grant
- Patent Title: Vertical tunneling field-effect transistors
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Application No.: US17745822Application Date: 2022-05-16
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Publication No.: US11862715B2Publication Date: 2024-01-02
- Inventor: Cheng-Ying Huang , Jack Kavalieros , Ian Young , Matthew Metz , Willy Rachmady , Uygar Avci , Ashish Agrawal , Benjamin Chu-Kung
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Essential Patents Group, LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/417 ; H01L29/786

Abstract:
Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of lateral TFETs.
Public/Granted literature
- US20220278227A1 VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS Public/Granted day:2022-09-01
Information query
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