- Patent Title: Semiconductor structure and endurance test method using the same
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Application No.: US17574629Application Date: 2022-01-13
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Publication No.: US11869613B2Publication Date: 2024-01-09
- Inventor: Wei-Chih Chien , Hsiang-Lan Lung
- Applicant: MACRONIX INTERNATIONAL CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee: MACRONIX INTERNATIONAL CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: G11C29/12
- IPC: G11C29/12 ; G11C11/402

Abstract:
A semiconductor structure is provided. The semiconductor structure includes a transistor and a memory device. The transistor includes a source, a drain, and a gate. The memory device is disposed at a drain side of the transistor and coupled to the drain. The memory device includes a first electrode, a switch layer, a memory layer, and a second electrode disposed sequentially. The first electrode is coupled to the drain.
Public/Granted literature
- US20230130293A1 SEMICONDUCTOR STRUCTURE AND ENDURANCE TEST METHOD USING THE SAME Public/Granted day:2023-04-27
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