Invention Grant
- Patent Title: Single crystalline silicon stack formation and bonding to a CMOS wafer
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Application No.: US17749282Application Date: 2022-05-20
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Publication No.: US11869803B2Publication Date: 2024-01-09
- Inventor: Si-Woo Lee , Byung Yoon Kim
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02 ; H01L25/18 ; H01L25/00

Abstract:
Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.
Public/Granted literature
- US20220277987A1 SINGLE CRYSTALLINE SILICON STACK FORMATION AND BONDING TO A CMOS WAFER Public/Granted day:2022-09-01
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