- Patent Title: Chip-stacked semiconductor package and method of manufacturing same
-
Application No.: US17733411Application Date: 2022-04-29
-
Publication No.: US11869818B2Publication Date: 2024-01-09
- Inventor: Hyoeun Kim , Yonghoe Cho , Sunkyoung Seo , Seunghoon Yeon , Sanguk Han
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Sughrue Mion, PLLC
- Priority: KR 20190075789 2019.06.25
- The original application number of the division: US16749620 2020.01.22
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L25/065 ; H01L23/31 ; H01L25/00 ; H01L23/00 ; G01R31/28 ; G01R27/26

Abstract:
A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.
Public/Granted literature
- US20220262689A1 CHIP-STACKED SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SAME Public/Granted day:2022-08-18
Information query
IPC分类: