Invention Grant
- Patent Title: Wiring formation method, method for manufacturing semiconductor device, and semiconductor device
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Application No.: US17009693Application Date: 2020-09-01
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Publication No.: US11869866B2Publication Date: 2024-01-09
- Inventor: Ryoichi Suzuki , Hirokazu Kato
- Applicant: KIOXIA CORPORATION
- Applicant Address: JP Tokyo
- Assignee: Kioxia Corporation
- Current Assignee: Kioxia Corporation
- Current Assignee Address: JP Tokyo
- Agency: Kim & Stewart LLP
- Priority: JP 20043282 2020.03.12
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/498 ; H01L21/768 ; H01L23/522 ; H01L23/528 ; H01L21/3213
Abstract:
According to one embodiment, a wiring fabrication method includes pressing a first template including a first recessed portion and a second recessed portion provided at a bottom of the first recessed portion against a first film to form a first pattern including a first raised portion, corresponding to the first recessed portion, and a second raised portion, corresponding to the second recessed portion. The second raised portion protrudes from the first raised portion once formed. After forming the first pattern, a first wiring, corresponding to the first raised portion, and a via, corresponding to the second raised portion, is formed using the first pattern.
Public/Granted literature
- US20210288017A1 WIRING FABRICATION METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE Public/Granted day:2021-09-16
Information query
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