A thin film transistor array substrate includes a substrate, at least one thin film transistor, a capacitor, an interlayer insulating layer, and a node connection line. The at least one thin film transistor is on the substrate. The capacitor is on the substrate and includes: a bottom electrode on the substrate; a top electrode overlapping the bottom electrode, the top electrode including an opening having a single closed curve shape; and a dielectric layer between the bottom electrode and the top electrode. The interlayer insulating layer covers the capacitor. The node connection line is on the interlayer insulating layer and electrically connects the capacitor to the least one thin film transistor. An overlapping area of the bottom electrode and the top electrode is divided by the opening into two separate areas.