Invention Grant
- Patent Title: Reduced-form-factor transistor with self-aligned terminals and adjustable on/off-currents and manufacture method thereof
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Application No.: US16388836Application Date: 2019-04-18
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Publication No.: US11869972B2Publication Date: 2024-01-09
- Inventor: Chao-Chun Lu
- Applicant: Etron Technology, Inc.
- Applicant Address: TW Hsinchu
- Assignee: Etron Technology, Inc.,Invention And Collaboration Laboratory Pte. Ltd.
- Current Assignee: Etron Technology, Inc.,Invention And Collaboration Laboratory Pte. Ltd.
- Current Assignee Address: TW Hsinchu; SG Singapore
- Agent Winston Hsu
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/10 ; H01L29/08 ; H01L29/06 ; H01L29/66 ; H01L21/762 ; H01L21/02 ; H01L29/417 ; H01L29/40 ; H01L21/3213 ; H01L21/265 ; H01L29/49 ; H01L21/311
Abstract:
A transistor structure includes a gate structure, a channel region, a drain region and a source region. The gate structure is positioned above a silicon surface of a first silicon material, the channel region is under the silicon surface, and the channel region includes a first terminal and a second terminal. The drain/source region is independent and not derived from the first silicon material, the drain region includes a first predetermined physical boundary directly connected to the first terminal of the channel region, and the source region includes a second predetermined physical boundary directly connected to the second terminal of the channel region. The drain/source region includes a lower portion below the silicon surface and the bottom of the lower portion of the drain/source region is confined to an isolator, and sidewalls of the drain/source region are confined to spacers except sidewalls of the lower portion of the drain/source region.
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