High speed, low quiescent current comparator
Abstract:
An integrated circuit device includes: an input stage configured to receive first and a second input signals and generate a first voltage based on the first input signal and generate a second voltage based on the second input signal; an amplification stage configured to generate a first output current based on the first voltage and a second output current based on the second voltage; a bias stage configured to generate a bias voltage for the amplification stage based on the first and second voltages; a load stage configured to output a differential voltage signal proportional to a current through a device for which current is sensed based on a comparison of the first and second output currents; and an output stage configured to output a signal to control a duty cycle of the device for which current is sensed.
Information query
Patent Agency Ranking
0/0