A system for testing a semiconductor may include a transfer chamber, at least one loadlock chamber and at least one test chamber. The transfer chamber may include a plurality of sidewalls. The loadlock chamber may be arranged on a first sidewall of the sidewalls of the transfer chamber. The loadlock chamber may include a carrier configured to receive a plurality of wafers. The test chamber may be arranged on a second sidewall of the sidewalls of the transfer chamber. When the transfer chamber is connected to the loadlock chamber, a pressure of the transfer chamber may be changed into a pressure of the loadlock chamber. When the transfer chamber is connected to the test chamber, the pressure of the transfer chamber may be changed into a pressure of the test chamber.