Invention Grant
- Patent Title: Characterizing error correlation based on error logging for computer buses
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Application No.: US16947558Application Date: 2020-08-06
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Publication No.: US11886312B2Publication Date: 2024-01-30
- Inventor: Debendra Das Sharma
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/30 ; G06F11/34 ; G06F11/07 ; G06F11/10

Abstract:
Systems and devices can include forward error correction (FEC) logic to identify a correctable error in the first flit, and correct the correctable error using three error correcting code (ECC) groups. System and devices can also include an error log, the correctable error log to log a symbol number in the first flit corrected by each ECC group, and to log a magnitude of the correctable error corrected by each ECC group in the first flit; and a configuration register to log link error correlation, the link error correlation comprising a indication of one or more bits in error in the first flit.
Information query