A circuit for testing a memory and a test method thereof are provided. According to the circuit for testing a memory provided by the present disclosure, a switch control circuit is connected between a discharge end and a negative bias signal end of a Sub Wordline Drive (SWD) and configured to input a trigger signal, so that potential of a Word Line (WL) signal end in a to-be-tested circuit meets a preset potential suspension range. Then, it is determined whether there is leakage behavior between the WL signal end and a Bit Line (BL) signal end in the to-be-tested circuit by detecting whether the present level state of a stored signal in the to-be-tested circuit is consistent with an initial level state. The to-be-tested circuit is a corresponding circuit in a single memory.