Invention Grant
- Patent Title: Inter-processor data transfer in a machine learning accelerator, using statically scheduled instructions
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Application No.: US16865226Application Date: 2020-05-01
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Publication No.: US11886981B2Publication Date: 2024-01-30
- Inventor: Nishit Shah , Srivathsa Dhruvanarayan , Reed Kotler
- Applicant: SiMa Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: SiMa Technologies, Inc.
- Current Assignee: SiMa Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Fenwick & West LLP
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G06N3/08

Abstract:
A compiler generates a computer program implementing a machine learning network on a machine learning accelerator (MLA) including interconnected processing elements. The computer program includes data transfer instructions for non-colliding data transfers between the processing elements. To generate the data transfer instructions, the compiler determines non-conflicting data transfer paths for data transfers based on a topology of the interconnections between processing elements, on dependencies of the instructions and on a duration for execution of the instructions. Each data transfer path specifies a routing and a time slot for the data transfer. The compiler generates data transfer instructions that specify routing of the data transfers and generates a static schedule that schedules execution of the data transfer instructions during the time slots for the data transfers. The static schedule also schedules execution of compute instructions for computations using transferred data that implement the machine learning network.
Public/Granted literature
- US20210342673A1 INTER-PROCESSOR DATA TRANSFER IN A MACHINE LEARNING ACCELERATOR, USING STATICALLY SCHEDULED INSTRUCTIONS Public/Granted day:2021-11-04
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