Invention Grant
- Patent Title: Memory for improving efficiency of error correction
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Application No.: US17523669Application Date: 2021-11-10
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Publication No.: US11887656B2Publication Date: 2024-01-30
- Inventor: Min Soo Yoo , Eun Hyup Doh
- Applicant: SK hynix Inc.
- Applicant Address: KR Gyeonggi-do
- Assignee: SK hynix Inc.
- Current Assignee: SK hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: IP & T GROUP LLP
- Priority: KR 20210078734 2021.06.17
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/4091 ; G11C11/4096 ; G11C11/4094 ; G11C11/408

Abstract:
A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.
Public/Granted literature
- US20220406362A1 MEMORY Public/Granted day:2022-12-22
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