Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.