Invention Grant
- Patent Title: Method for producing three-dimensional structure, method for producing vertical transistor, vertical transistor wafer, and vertical transistor substrate
-
Application No.: US17488883Application Date: 2021-09-29
-
Publication No.: US11887845B2Publication Date: 2024-01-30
- Inventor: Kazutaka Kamijo , Etsuo Fukuda , Takashi Ishikawa , Koji Izunome , Moriya Miyashita , Takao Sakamoto , Tetsuo Endoh
- Applicant: GLOBALWAFERS JAPAN CO., LTD. , TOHOKU UNIVERSITY
- Applicant Address: JP Niigata
- Assignee: GLOBALWAFERS JAPAN CO., LTD.,TOHOKU UNIVERSITY
- Current Assignee: GLOBALWAFERS JAPAN CO., LTD.,TOHOKU UNIVERSITY
- Current Assignee Address: JP Niigata; JP Sendai
- Agency: Oliff PLC
- Priority: JP 17140079 2017.07.19
- The original application number of the division: US16632607
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/66

Abstract:
A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.
Public/Granted literature
Information query
IPC分类: