Invention Grant
- Patent Title: High precision 3D metal stacking for a plurality of 3D devices
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Application No.: US17237628Application Date: 2021-04-22
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Publication No.: US11887897B2Publication Date: 2024-01-30
- Inventor: Mark I. Gardner , H. Jim Fulford
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/66 ; H01L29/78 ; H01L29/786 ; H01L29/417 ; H01L21/822 ; H01L29/06

Abstract:
Aspects of the present disclosure provide a method of fabricating a semiconductor device. For example, the method can include providing a substrate. The substrate can include a first type region and a second type region. The method can also include forming a multilayer stack on the substrate. The multilayer stack can include alternate metal layers and dielectric layers. The method can also include forming first and second openings through the multilayer stack to uncover the first and second type regions, respectively. The method can also include forming first and second vertical channel structures within the first and second openings, respectively. Each of the first and second vertical channel structures can have source, gate and drain regions being in contact with vertical sidewalls of the metal layers of the multilayer stack uncovered by a respective one of the first and second openings.
Public/Granted literature
- US20220139786A1 HIGH PRECISION 3D METAL STACKING FOR A PLURALITY OF 3D DEVICES Public/Granted day:2022-05-05
Information query
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