Invention Grant
- Patent Title: Semiconductor device manufacturing method
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Application No.: US17287922Application Date: 2019-10-18
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Publication No.: US11887975B2Publication Date: 2024-01-30
- Inventor: Naoko Tsuji
- Applicant: DAICEL CORPORATION
- Applicant Address: JP Osaka
- Assignee: DAICEL CORPORATION
- Current Assignee: DAICEL CORPORATION
- Current Assignee Address: JP Osaka
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: JP 18199011 2018.10.23 JP 18199012 2018.10.23
- International Application: PCT/JP2019/041197 2019.10.18
- International Announcement: WO2020/085257A 2020.04.30
- Date entered country: 2021-04-22
- Main IPC: H01L21/683
- IPC: H01L21/683 ; H01L25/00 ; H01L23/00 ; H01L21/304 ; H01L21/768 ; H01L25/065

Abstract:
Provided is a semiconductor device manufacturing method in which semiconductor elements are formed into multiple layers through the lamination of wafers in which the semiconductor elements are fabricated, the method being suited for efficiently creating multiple layers of thin wafers while suppressing warping of a wafer laminate. The method of the present invention includes a preparation step, a thinning step, a bonding step, a removal step, and a multilayering step. In the preparation step, a reinforced wafer is prepared, the reinforced wafer having a laminated structure that includes: a wafer including an element forming surface and a back surface opposite from the element forming surface; a supporting substrate; and a temporary adhesive layer for forming temporary adhesion, the temporary adhesive layer being provided between the element forming surface side of the wafer and the supporting substrate.
Public/Granted literature
- US20210384184A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2021-12-09
Information query
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