The present application discloses a capacitor integrated in a FinFET. The capacitor and a resistor are both integrated in a middle-end-of-line process layer. A resistor main body layer and a resistor cover layer of the resistor and the forming regions of the intermediate dielectric layer and the lower electrode plate of the capacitor are patterned in a lithography process applying a first photomask; a forming region of an upper electrode plate is patterned in another lithography process applying a second photomask; the lower electrode plate, the upper electrode plate and the resistor main body layer are respectively connected with a metal zeroth layer. The present application further discloses a method for fabricating a capacitor integrated in a FinFET device. The disclosed method can reduce the process cost and improve the process efficiency, as well as flexibly select the capacitance of the capacitor by the process.