Invention Grant
- Patent Title: Semiconductor wafer with devices having different top layer thicknesses
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Application No.: US17827636Application Date: 2022-05-27
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Publication No.: US11887987B2Publication Date: 2024-01-30
- Inventor: Gulbagh Singh , Kuan-Liang Liu , Wang Po-Jen , Kun-Tsang Chuang , Hsin-Chi Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: FOLEV & LARDNER LLP
- The original application number of the division: US16851345 2020.04.17
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L21/02 ; H01L21/304 ; H01L21/306 ; H01L21/3105 ; H01L21/762 ; H01L21/84

Abstract:
A circuit includes a base silicon layer, a base oxide layer, a first top silicon layer, a second top silicon layer, a first semiconductor device, and a second semiconductor device. The base oxide layer is formed over the base silicon layer. The first top silicon layer is formed over a first region of the base oxide layer and has a first thickness. The second top silicon layer is formed over a second region of the base oxide layer and has a second thickness less than the first thickness. The first semiconductor device is formed over the first top silicon layer and the second semiconductor device is formed over the second top silicon layer. The ability to fabricate a top silicon layers with differing thicknesses can provide a single substrate having devices with different characteristics, such as having both fully depleted and partially depleted devices on a single substrate.
Public/Granted literature
- US20220285403A1 SEMICONDUCTOR WAFER WITH DEVICES HAVING DIFFERENT TOP LAYER THICKNESSES Public/Granted day:2022-09-08
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