Invention Grant
- Patent Title: Dielectric isolation structure for multi-gate transistors
-
Application No.: US18077714Application Date: 2022-12-08
-
Publication No.: US11888049B2Publication Date: 2024-01-30
- Inventor: Jen-Hong Chang , Yuan-Ching Peng , Chung-Ting Ko , Kuo-Yi Chao , Chia-Cheng Chao , You-Ting Lin , Chih-Chung Chang , Yi-Hsiu Liu , Jiun-Ming Kuo , Sung-En Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- The original application number of the division: US17359105 2021.06.25
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L29/66 ; H01L21/8234 ; H01L29/06 ; H01L29/78

Abstract:
Semiconductor structures and methods of forming the same are provided. A method according to the present disclosure includes forming a stack of epitaxial layers over a substrate, forming a first fin-like structure and a second fin-like structure from the stack, forming an isolation feature between the first fin-like structure and the second fin-like structure, forming a cladding layer over the first fin-like structure and the second fin-like structure, conformally depositing a first dielectric layer over the cladding layer, depositing a second dielectric layer over the first dielectric layer, planarizing the first dielectric layer and the second dielectric layer until the cladding layer are exposed, performing an etch process to etch the second dielectric layer to form a helmet recess, performing a trimming process to trim the first dielectric layer to widen the helmet recess, and depositing a helmet feature in the widened helmet recess.
Public/Granted literature
- US20230098409A1 DIELECTRIC ISOLATION STRUCTURE FOR MULTI-GATE TRANSISTORS Public/Granted day:2023-03-30
Information query
IPC分类: