Invention Grant
- Patent Title: Analog multiplexer circuit and analog-digital conversion system
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Application No.: US17768168Application Date: 2019-10-23
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Publication No.: US11888495B2Publication Date: 2024-01-30
- Inventor: Munehiko Nagatani , Teruo Jo , Hiroshi Yamazaki , Hideyuki Nosaka
- Applicant: Nippon Telegraph and Telephone Corporation
- Applicant Address: JP Tokyo
- Assignee: Nippon Telegraph and Telephone Corporation
- Current Assignee: Nippon Telegraph and Telephone Corporation
- Current Assignee Address: JP Tokyo
- Agency: Slater Matsil, LLP
- International Application: PCT/JP2019/041475 2019.10.23
- International Announcement: WO2021/079426A 2021.04.29
- Date entered country: 2022-04-11
- Main IPC: H03M1/12
- IPC: H03M1/12 ; H03K17/693
Abstract:
An analog demultiplexer circuit includes a clock distribution circuit that outputs clock signals (CK1P and CK1N) and clock signals (CK2P and CK2N) complementary thereto, a track-and-hold circuit that holds analog input signals (VINP and VINN) in synchronization with the clock signals (CK1P and CK1N), and a track-and-hold circuit that holds the analog input signals (VINP and VINN) in synchronization with the clock signals (CK2P and CK2N).
Public/Granted literature
- US20230336185A1 Analog Multiplexer Circuit and Analog-Digital Conversion System Public/Granted day:2023-10-19
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