A multicycle path circuit capable of operating at a functional mode and an at-speed test mode. The multicycle path circuit includes an on-chip controller configured to receive an on-chip clock signal and modulate the on-chip clock signal to provide a first clock signal to a first circuit and a second clock signal to a second circuit. The first clock signal and the second clock signal are in a multicycle phase relationship. The on-chip controller is configured to ensure the clock paths to and from the second circuit to be the same for the functional mode and the at-speed test mode and therefore to avoid hold and setup timing conflict between these modes.