A system can include: a plurality of processing Cores; a Package Interconnect communicatively coupled with the plurality of processing Cores; a Configurable LFSR PRV Generator Hardware Array means communicatively coupled with the Package Interconnect; a Galois Multiplication Hardware Accelerator means communicatively coupled with the Package Interconnect; an Extended Euclidian Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect; and a Fischer-Yates Shuffle Algorithm Hardware Accelerator means communicatively coupled with the Package Interconnect.