A gate driving circuit and a display panel are provided. The gate driving circuit includes M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers are respectively connected to the N clock signal lines, where N is an even number greater than or equal to 4, and M is an integer greater than or equal to N; a signal output terminal (OUTPUT) of an ith shift register is connected to a signal input terminal (INPUT) of a (i+p)th shift register, where (N−4)/2≤p≤N/2, and i is taken from 1 to (M−p); and a pull-up reset signal terminal of a jth shift register is connected to a signal output terminal (OUTPUT) of a (j+q)th shift register, where 1