Invention Grant
- Patent Title: Dual performance trim for optimization of non-volatile memory performance, endurance, and reliability
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Application No.: US17704434Application Date: 2022-03-25
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Publication No.: US11894060B2Publication Date: 2024-02-06
- Inventor: Ajay Shyam Manwani
- Applicant: Western Digital Technologies, Inc.
- Applicant Address: US CA San Jose
- Assignee: Western Digital Technologies, Inc.
- Current Assignee: Western Digital Technologies, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vierra Magen Marcus LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G11C16/10 ; G11C16/04 ; G11C16/34 ; G06F3/06 ; G11C11/56 ; H01L25/065 ; H10B43/27

Abstract:
A non-volatile memory operates in a high perform mode when writing host data by using a first programming algorithm. When performing background operations, the non-volatile memory writes data using a lower performance, but higher endurance programming algorithm. In both cases the data is written in the same multi-level format, but the higher endurance programming algorithm uses, for example, a staircase waveform with a smaller step size. A count is kept for the number of program/erase cycles for memory blocks for both types of programming trim, but where a high performance write is weighted more heavily than a high endurance write.
Public/Granted literature
- US20230307054A1 DUAL PERFORMANCE TRIM FOR OPTIMIZATION OF NON-VOLATILE MEMORY PERFORMANCE, ENDURANCE, AND RELIABILITY Public/Granted day:2023-09-28
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