- Patent Title: Method for fabricating semiconductor device with covering liners
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Application No.: US17716117Application Date: 2022-04-08
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Publication No.: US11894264B2Publication Date: 2024-02-06
- Inventor: Tse-Yao Huang
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US16902692 2020.06.16
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/532 ; H01L23/528 ; H10B12/00

Abstract:
The present application discloses provides a method for fabricating a semiconductor device. The method includes providing a substrate, forming a sacrificial structure above the substrate, forming a supporting liner covering the sacrificial structure, forming an energy-removable layer covering the supporting liner, performing a planarization process until a top surface of the sacrificial structure is exposed, performing an etch process to remove the sacrificial structure and concurrently form a first opening in the energy-removable layer, forming covering liners on sidewalls of the first opening and on a top surface of the energy-removable layer, forming a first conductive feature in the first opening, and applying an energy source to turn the energy-removable layer into a porous insulating layer.
Public/Granted literature
- US20220230913A1 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH COVERING LINERS Public/Granted day:2022-07-21
Information query
IPC分类: