Invention Grant
- Patent Title: Semiconductor package with through vias and stacked redistribution layers and manufacturing method thereof
-
Application No.: US17164851Application Date: 2021-02-02
-
Publication No.: US11894341B2Publication Date: 2024-02-06
- Inventor: Tsung-Ding Wang , Yen-Fu Su , Hao-Cheng Hou , Jung-Wei Cheng , Chien-Hsun Lee , Hsin-Yu Pan
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L21/48 ; H01L21/56 ; H01L23/31 ; H01L23/538 ; H01L25/00 ; H01L23/498 ; H01L23/00 ; H01L21/683

Abstract:
A semiconductor package includes a semiconductor die, an encapsulant, a first and second dielectric layer, a through via, an extension pad, and a routing via. The semiconductor die includes a contact post. The first dielectric layer extends on the encapsulant. The through via extends through the first dielectric layer and has one end contacting the contact post. The extension pad is disposed on the first dielectric layer, contacting an opposite end of the through via with respect to the contact post. The extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant. The second dielectric layer is disposed on the first dielectric layer and the extension pad. The routing via extends through the second dielectric layer to contact the second end of the extension pad.
Public/Granted literature
- US20210242172A1 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2021-08-05
Information query
IPC分类: