Invention Grant
- Patent Title: System-level packaging structure and method for LED chip
-
Application No.: US17471574Application Date: 2021-09-10
-
Publication No.: US11894357B2Publication Date: 2024-02-06
- Inventor: Yenheng Chen , Chengchung Lin
- Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Applicant Address: CN Jiangyin
- Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee Address: CN Jiangyin
- Agency: Alston & Bird LLP
- Priority: CN 2010947512.4 2020.09.10 CN 2021970939.8 2020.09.10
- Main IPC: H01L25/18
- IPC: H01L25/18 ; H01L23/31 ; H01L23/538 ; H01L23/00 ; H01L33/62 ; H01L33/54 ; H01L23/42 ; H01L21/56 ; H01L21/78 ; H01L21/48 ; H01L23/367

Abstract:
The present invention provides a SiP structure and method for a light emitting diode (LED) chip. The packaging structure includes: a heat sink structure, a first chip, a first packaging layer, a second packaging layer, a rewiring layer, an LED chip, a printed circuit board (PCB), and a third packaging layer. In the present invention, chips with a plurality of functions, including the first chip, the LED chip, and the like, are integrated into one packaging structure through fan-out system-level packaging, to meet a plurality of different system functional requirements and improve the performance of the packaging system. By the rewiring layer, a metal connecting pillar, a metal lead wire, and the like, the first chip, the LED chip, and the PCB are electrically connected, to achieve a three-dimensional vertically stacked package thereby effectively reducing the area of a SiP and improving the integration of the packaging system.
Public/Granted literature
- US20220077132A1 SYSTEM-LEVEL PACKAGING STRUCTURE AND METHOD FOR LED CHIP Public/Granted day:2022-03-10
Information query
IPC分类: