Invention Grant
- Patent Title: Integrated circuit including dipole incorporation for threshold voltage tuning in transistors
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Application No.: US17370843Application Date: 2021-07-08
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Publication No.: US11894367B2Publication Date: 2024-02-06
- Inventor: Lung-Kun Chu , Mao-Lin Huang , Chung-Wei Hsu , Jia-Ni Yu , Kuo-Cheng Chiang , Kuan-Lun Cheng , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Seed IP Law Group LLP
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L29/423 ; H01L21/8234 ; H01L29/786 ; H01L29/06

Abstract:
A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
Public/Granted literature
- US20230010502A1 INTEGRATED CIRCUIT INCLUDING DIPOLE INCORPORATION FOR THRESHOLD VOLTAGE TUNING IN TRANSISTORS Public/Granted day:2023-01-12
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