Invention Grant
- Patent Title: Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance
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Application No.: US17727249Application Date: 2022-04-22
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Publication No.: US11894378B2Publication Date: 2024-02-06
- Inventor: H. Jim Fulford , Mark I. Gardner
- Applicant: Tokyo Electron Limited
- Applicant Address: JP Tokyo
- Assignee: Tokyo Electron Limited
- Current Assignee: Tokyo Electron Limited
- Current Assignee Address: JP Tokyo
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- The original application number of the division: US16591134 2019.10.02
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L27/088 ; H01L21/822 ; H01L21/8238
Abstract:
A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.
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Information query
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