Invention Grant
- Patent Title: Semiconductor device
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Application No.: US17279153Application Date: 2019-09-27
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Publication No.: US11894466B2Publication Date: 2024-02-06
- Inventor: Rai Sato , Masami Jintyou , Masayoshi Dobashi , Takashi Shiraishi , Satoru Saito , Yasutaka Nakazawa
- Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
- Applicant Address: JP Atsugi
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi
- Agency: Fish & Richardson P.C.
- Priority: JP 18192125 2018.10.10
- International Application: PCT/IB2019/058211 2019.09.27
- International Announcement: WO2020/074993A 2020.04.16
- Date entered country: 2021-03-24
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/423 ; H01L29/66 ; H01L27/12 ; H01L29/49

Abstract:
A semiconductor device with favorable electrical characteristics is provided. A highly reliable semiconductor device is provided. The semiconductor device includes a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, and a conductive layer; the first insulating layer, the metal oxide layer, and the conductive layer are stacked in this order over the semiconductor layer; an end portion of the first insulating layer is located inward from an end portion of the semiconductor layer; an end portion of the metal oxide layer is located inward from the end portion of the first insulating layer; and an end portion of the conductive layer is located inward from the end portion of the metal oxide layer. The second insulating layer is preferably provided to cover the semiconductor layer, the first insulating layer, the metal oxide layer, and the conductive layer. It is preferable that the semiconductor layer include a first region, a pair of second regions, and a pair of third regions; the first region overlap with the first insulating layer and the metal oxide layer; the second regions between which the first region is sandwiched overlap with the first insulating layer and not overlap with the metal oxide layer; the third regions between which the first region and the pair of second regions are sandwiched not overlap with the first insulating layer; and the third regions be in contact with the second insulating layer.
Public/Granted literature
- US20210399140A1 SEMICONDUCTOR DEVICE Public/Granted day:2021-12-23
Information query
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