- Patent Title: Method for preparing semiconductor device structure with air gap
-
Application No.: US17503662Application Date: 2021-10-18
-
Publication No.: US11895826B2Publication Date: 2024-02-06
- Inventor: Chin-Te Kuo
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- The original application number of the division: US16654497 2019.10.16
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L27/108 ; H10B12/00 ; H01L21/762 ; H01L21/764

Abstract:
A method for preparing a semiconductor device structure includes forming a first fin structure and a second fin structure over a semiconductor substrate, forming an isolation structure over the semiconductor substrate, partially removing the first fin structure and the second fin structure to form a recessed portion of the first fin structure and a recessed portion of the second fin structure, epitaxially growing a first source/drain (S/D) structure over the recessed portion of the first fin structure and a second S/D structure over the recessed portion of the second fin structure, partially removing the isolation structure through the first opening to form a second opening, and forming a contact etch stop layer (CESL) over the first S/D structure and the second S/D structure such that an air gap is formed and sealed in the first opening and the second opening.
Public/Granted literature
- US20220037331A1 METHOD FOR PREPARING SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP Public/Granted day:2022-02-03
Information query
IPC分类: