Invention Grant
- Patent Title: Method of manufacturing semiconductor structure having tapered bit line
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Application No.: US17837718Application Date: 2022-06-10
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Publication No.: US11895829B2Publication Date: 2024-02-06
- Inventor: Pei-Rou Jiang , Chao-Wen Lay
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: MUNCY, GEISSLER, OLDS & LOWE, P.C.
- Main IPC: H10B12/00
- IPC: H10B12/00

Abstract:
The present disclosure provides a method of manufacturing a semiconductor structure. The method includes: providing a substrate; forming a bit line structure over the substrate; forming a spacer surrounding the bit line structure; forming a polysilicon layer covering the bit line structure and the spacer; performing a first etching operation on the polysilicon layer to obtain a first height of the polysilicon layer, wherein the first height is less than a height of the bit line structure or a height of the spacer; performing a second etching operation on a first portion of the spacer; and performing a third etching operation on the polysilicon layer to obtain a second height of the polysilicon layer, wherein the second height is less than the first height.
Public/Granted literature
- US20230403846A1 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE HAVING TAPERED BIT LINE Public/Granted day:2023-12-14
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