A method to reverse source data in a processor in response to a vector reverse instruction includes specifying, in respective fields of the vector reverse instruction, a source register containing the source data and a destination register. The source register includes a plurality of lanes and each lane contains a data element, and the destination register includes a plurality of lanes corresponding to the lanes of the source register. The method further includes executing the vector reverse instruction by creating reversed source data by reversing the order of the data elements, and storing the reversed source data in the destination register.