Invention Grant
- Patent Title: Variable clock adaptation in neural network processors
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Application No.: US17023144Application Date: 2020-09-16
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Publication No.: US11900240B2Publication Date: 2024-02-13
- Inventor: Nitin Chawla , Giuseppe Desoli , Manuj Ayodhyawasi , Thomas Boesch , Surinder Pal Singh
- Applicant: STMICROELECTRONICS S.r.l. , STMicroelectronics International N.V.
- Applicant Address: IT Agrate Brianza
- Assignee: STMICROELECTRONICS S.r.l.,STMicroelectronics International N.V.
- Current Assignee: STMICROELECTRONICS S.r.l.,STMicroelectronics International N.V.
- Current Assignee Address: IT Agrate Brianza; CH Geneva
- Agency: Seed IP Law Group LLP
- Main IPC: G06N3/06
- IPC: G06N3/06 ; G06F1/32 ; G06F9/50 ; G06F1/08 ; G06N3/063 ; G06N3/082 ; G06F1/3228 ; G06F1/324 ; G06F1/3296

Abstract:
Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.
Public/Granted literature
- US20210081773A1 VARIABLE CLOCK ADAPTATION IN NEURAL NETWORK PROCESSORS Public/Granted day:2021-03-18
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