Invention Grant
- Patent Title: Tile sequencing mechanism
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Application No.: US17590521Application Date: 2022-02-01
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Publication No.: US11900539B2Publication Date: 2024-02-13
- Inventor: Subramaniam Maiyuran , Saurabh Sharma , Jorge F. Garcia Pabon , Raghavendra Kamath Miyar , Sudheendra Srivathsa , Justin Decell , Aditya Navale
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jaffery Watson Mendonsa & Hamilton LLP
- Main IPC: G06T15/00
- IPC: G06T15/00 ; G06T17/20 ; G06T1/20

Abstract:
An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises sequencer hardware to operate in a tile mode to render objects, including performing batch formation to generate one or more batches of received objects, performing tile sequencing for each of the objects to compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects.
Public/Granted literature
- US20220262070A1 TILE SEQUENCING MECHANISM Public/Granted day:2022-08-18
Information query
IPC分类:
G | 物理 |
G06 | 计算;推算或计数 |
G06T | 一般的图像数据处理或产生 |
G06T15/00 | 3D〔三维〕图像的加工 |