The memory device includes a plurality of memory cell that arranged in an array, which includes a plurality of channels that are in electrical communication with a source line. The memory device also includes a controller that is configured to erase the memory cells in at least one erase pulse. During the at least one erase pulse, the controller is configured to drive the source line to an elevated voltage that is equal to an erase voltage Vera plus a kick voltage V_kick for a duration t_kick. The controller is then configured to reduce the voltage of the source line to the erase voltage Vera such that a voltage of the channel remains elevated during the entire erase pulse, including after the voltage of the source line has been reduced to the erase voltage Vera.