Invention Grant
- Patent Title: Self-aligned scheme for semiconductor device and method of forming the same
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Application No.: US17371416Application Date: 2021-07-09
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Publication No.: US11901228B2Publication Date: 2024-02-13
- Inventor: Cai-Ling Wu , Hsiu-Wen Hsueh , Wei-Ren Wang , Po-Hsiang Huang , Chii-Ping Chen , Jen Hung Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/535 ; H01L23/532

Abstract:
In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.
Public/Granted literature
- US20220319922A1 Self-Aligned Scheme for Semiconductor Device and Method of Forming the Same Public/Granted day:2022-10-06
Information query
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