Invention Grant
- Patent Title: Semiconductor structure with gate-all-around devices and stacked FinFET devices
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Application No.: US17739925Application Date: 2022-05-09
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Publication No.: US11901236B2Publication Date: 2024-02-13
- Inventor: Feng-Ching Chu , Wei-Yang Lee , Chia-Pin Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/088 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L29/66 ; H01L21/02 ; H01L21/8238

Abstract:
An integrated circuit (IC) includes a substrate and a first transistor on the substrate. The first transistor includes two first source/drain features, a stack of first semiconductor layers and second semiconductor layers alternately stacked one over another and disposed between the two first source/drain features, a first gate dielectric layer disposed over top and sidewalls of the stack of the first and the second semiconductor layers, a first gate electrode layer disposed over the first gate dielectric layer, and first spacer features disposed laterally between each of the second semiconductor layers and each of the two first source/drain features and electrically isolating each of the second semiconductor layers from each of the two first source/drain features. The first semiconductor layers electrically connect the two first source/drain features.
Public/Granted literature
- US20220262683A1 SEMICONDUCTOR STRUCTURE WITH GATE-ALL-AROUND DEVICES AND STACKED FINFET DEVICES Public/Granted day:2022-08-18
Information query
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