Invention Grant
- Patent Title: Semiconductor structure and method for manufacturing semiconductor structure
-
Application No.: US17487697Application Date: 2021-09-28
-
Publication No.: US11901405B2Publication Date: 2024-02-13
- Inventor: Shuangshuang Wu
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Cooper Legal Group, LLC
- Priority: CN 2010956310.6 2020.09.11
- Main IPC: H10B12/00
- IPC: H10B12/00 ; H01L49/02

Abstract:
A method for manufacturing a semiconductor structure includes: a substrate is provided, in which the substrate includes an array region and a peripheral region adjacent to each other, and the array region includes a buffer region connected with the peripheral region; a first dielectric layer, a first supporting layer, a second dielectric layer, a second supporting layer and a third dielectric layer, which are successively stacked onto one another, are formed on the substrate; a groove-type lower electrode, which at least penetrates through the third dielectric layer and the second supporting layer, is formed in the buffer region; the third dielectric layer is removed through a wet etching process; and the second supporting layer in the peripheral region is etched after the third dielectric layer is removed.
Public/Granted literature
- US20220085152A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE Public/Granted day:2022-03-17
Information query