Invention Grant
- Patent Title: Diffusion barrier layer for source and drain structures to increase transistor performance
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Application No.: US17869874Application Date: 2022-07-21
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Publication No.: US11901413B2Publication Date: 2024-02-13
- Inventor: Kuei-Ming Chen , Chi-Ming Chen , Chung-Yi Yu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- The original application number of the division: US17064811 2020.10.07
- Main IPC: H01L21/84
- IPC: H01L21/84 ; H01L27/088 ; H01L27/12 ; H01L29/167 ; H01L29/66 ; H01L21/02 ; H01L29/417 ; H01L21/8238 ; H01L27/092 ; B82Y10/00 ; H01L29/06 ; H01L29/786 ; H01L29/165 ; H01L29/423 ; H01L29/775 ; H01L29/78 ; H01L21/8234 ; H01L29/10 ; H01L29/08

Abstract:
Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.
Public/Granted literature
- US20220367631A1 DIFFUSION BARRIER LAYER FOR SOURCE AND DRAIN STRUCTURES TO INCREASE TRANSISTOR PERFORMANCE Public/Granted day:2022-11-17
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