A method of forming an electrical device that includes forming a multilayered fin composed of a first source/drain layer for a first transistor, a first channel layer for the first transistor, a common source/drain layer for the first transistor and a second transistor, a second channel layer for the second transistor and a second source/drain layer for the second transistor. A common spacer is formed on the common source/drain layer that separates a first opening to the first channel layer from a second opening to the second channel layer. Gate structures are then formed in the first and second openings.