Invention Grant
- Patent Title: Phase locked loop circuit with increased robustness
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Application No.: US17792772Application Date: 2020-01-21
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Publication No.: US11902410B2Publication Date: 2024-02-13
- Inventor: Henrik Sjöland
- Applicant: Telefonaktiebolaget LM Ericsson (publ)
- Applicant Address: SE Stockholm
- Assignee: Telefonaktiebolaget LM Ericsson (publ)
- Current Assignee: Telefonaktiebolaget LM Ericsson (publ)
- Current Assignee Address: SE Stockholm
- Agency: Sage Patent Group
- International Application: PCT/SE2020/050050 2020.01.21
- International Announcement: WO2021/150150A 2021.07.29
- Date entered country: 2022-07-14
- Main IPC: H04L7/033
- IPC: H04L7/033 ; H03L7/093 ; H03L7/099

Abstract:
A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.
Public/Granted literature
- US20230046659A1 PHASE LOCKED LOOP CIRCUIT WITH INCREASED ROBUSTNESS Public/Granted day:2023-02-16
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