Phase locked loop circuit with increased robustness
Abstract:
A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.
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