The present disclosure achieves a display device provided with a pixel circuit that enables both high-frequency drive and low-frequency drive without causing deterioration in display quality. In a pixel circuit (20), a holding capacitor (C1) is provided between a second control node (NA) connected to a data signal line via a write control transistor (T3) and a first control node (NG) connected to a control terminal of a drive transistor (T4). An oxide thin-film transistor (TFT) is employed for each of a first initialization transistor (T1) having a second conductive terminal connected to the first control node (NG) and a threshold voltage compensation transistor (T2) having a first conductive terminal connected to the first control node (NG).